#include "cpu.h"


//31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 7 6 5 4 3 0
//cond 0 0 0 1 0 0 0 0 Rn Rd SBZ 1 0 0 1 Rm
bool CCPU::swp()
{
	__u32 temp;
	__u32 address;

	address=regfile.read_register(arm_insn.swp.Rn);

	//MemoryAccess(B-bit, E-bit)
	//processor_id = ExecutingProcessor()
	//if ConditionPassed(cond) then


	if(!mmu.read_int(address,&temp)) return false;
	//if (CP15_reg1_Ubit == 0) then
	if(mmu.cp15.ControlRegister().U==0)
	{
	//temp = Memory[address,4] Rotate_Right (8 * address[1:0])
	//Memory[address,4] = Rm
	//Rd = temp
		__u32 bits=(address&3)*8;
		temp=(temp>>bits)|(temp<<(32-bits));
	}
	//else /* CP15_reg1_Ubit ==1 */
	else
	{
	//temp = Memory[address,4]
	//Memory[address,4] = Rm
	//Rd = temp
	}

	if(!mmu.write_int(address,regfile.read_register(arm_insn.swp.Rm)))
		return false;

	regfile.write_register(arm_insn.swp.Rd,temp);

	//if Shared(address) then /* ARMv6 */
	{
	//physical_address = TLB(address)
	//ClearExclusiveByAddress(physical_address,processor_id,4)
	}
	return true;
}